Name: Digital Logic and computer architecture
Brand: MathsInDepth
SKU: 611e50e00cf2b3d77782a331
Price: 2500 INR
Availability: InStock

Test Series

Boolean Algebra

NUMBER SYSTEM

Note: This topic is common in many subjects like C, computer architecture etc. hence we are covering it in depth for your better understandung

Concept behind formation of Number System

Decimal To Binary-Octa-Hexa

Live Lecture: Number System Conversion

Quiz - Number System

Components of Computer System | Von-Neumann Architecture

Introduction

Introduction To Digital Gates

Boolean Algebra

Live Lecture: Boolean Law's

Live Lecture: Concept of Maxterm and Minterm Part 1

Live Lecture: Concept of Maxterm and Minterm Part 2

Live Lecture: Dual of a function and its properties

Live Lecture: Properties of XOR & XNOR

Live Lecture: Numerical Solving

Live Lecture: Concept of Functionally Complete Boolean Function

Live Lecture: Implementation of Boolean Functions using NAND and NOR

Assignment 1

Live Lecture: Functionally Complete Boolean Function

Functionally Complete Boolean Functions

Boolean Algebra Hand Written Notes (Jash)

Minimization

Concept of K MAP : PART 1

Concept of K MAP : PART 2

K MAP

K MAP EXAMPLES

Boolean Algebra and K MAP : Test 1

Advance Lecture : K MAP

DATA REPRESENTATION & ARITHMETIC ALGORITHM

Recording - Subtraction Using 2's and 1's complement

Recording - signed and unsigned number representation

Recording - Floating Point Representation

Recording - IEEE 754 number system

Encoding System : Grey,BCD,Excess-3, ASCII codes

NUMBER SYSTEM MAIN POINTS

Combinational Circuits

Design of Adder & Subtractor : Part 1

Design of Adder & Subtractor : Part 2

Time Complexity of Carry Look Ahead Adder & Introduction To MUX

Multiplexer Problem Solving

CONCEPT OF DEMUX, DECODER & ENCODER

Encoder-Decoder Notes

Implementation of ROM usind Decoder and Expansion of MUX

Combinational Circuit Assignment 1

Combinational Circuit Assignment 1 Solution

Comparator CKT

Comparator Circuit & Expansion of Decoder

Test 1: CMB

Test 2: CMB

Sequential Circuits

Introduction To Sequential Circuits

SR FLIP FLOP

JK Flip Flop

Concept of D, T Flip Flop & Flip Flop Conversion

Design of Synchronous Counter

Assignment 1

Assignment 1 Solution

Design of Asynchronous Counter

Test on cominational & sequential Circuits

MODULE 4: CONTROL UNIT DESIGN

Addressing Modes

MCQ's on Addressing

Various Special Purpose Registers and Fetch Cycle

Control Unit Design Part 1

Control Unit Design Part 2

MEMORY ORGANIZATION

NOTE: THESE ARE GATE VIDEOS BUT COVERS ENTIRE UNIVERSITY SYLLABUS IN DEPTH

Recording - Introduction To Cache Memory and Mapping Techniques

Cache Part 1

Cache Part 2

Cache Part 3

Cache Part 4

Introduction To Cache and Mapping Techniques

Global and Local Miss and Hit Rate

Average Access Time Calculation : Part 1

Average Access Time Calculation : Part 2

Tavg Calculation Using Miss Penalty

CPU Time Calculation

Cache Policies: Part 1

Cache Policies: Part 2 | Cache Replacement Algorithms

Implementation of LRU

Inclusive and Exclusive Cache

Write Policies

Unified vs Split Cache _ Blocking vs Non Blocking Cache

Types of Misses and Reducing Miss rate : Part 1

MEMORY ORGANIZATION BY SHRIKANT SIR

Memory Organization Part: 1

Memory organization: Part 2

PROBLEM SOLVING

MODULE 6: PIPELINING

Instruction Pipelining Part 1

Recording - Instruction Pipelining Part 2

Removing Name (anti and output) Dependency using Register Renaming

Solving RAW Data Hazard: Forwarding or By Passing

Load Delay Slot and Instruction Scheduling

Control Hazard Solution: Filling Branch Delay Slots

1 bit branch predictor

2 bit Branch Predictor

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Digital Logic and computer architecture

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